搜索资源列表
interleaver-vhdl.rar
- VHDL编写的基于FPGA的4-8交织器代码，有需要的下来看看,4-8 prepared VHDL code interleaver
convcode_interleaving.rar
- 一个实现了213卷积码编码和卷积交织的verilog程序，编译通过,An implementation of 213 convlution code and interleaving on verilog HDL.
FPGA_interleaver
- 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
pro_4d1
- 此代码可实现8bits 108M 4路BT656 像素交织输入转为8bits 108M 4路行交织的视频数据，并有仿真文件，在modelsim中运行即可。-This code can be realized 8bits 108M 4 way BT656 pixel interleaving input into 8bits 108M 4 way line of cutting the video data, and there are simulation files can be run in
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
4_31
- 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
top
- 交织的vhdl实现，希望对大家有帮助，同他学习！-VHDL-cutting to achieve, I hope all of you help with his learning!
fen_zu_interlacing
- 一个简单的交织实现程序，可以自己看看，具体功能很简单，如果看不懂的话可以留言哦，欢迎交流哦-Interwoven to achieve a simple procedure, can take a look at the specific function is very simple, If you do not know if can post Oh, welcomed the exchange of Oh
ENCODE
- 本源码实现交织编码，源码为VHDL语言。运行于发射端FPGA。-Interleaved Coded achieve this source, source code for VHDL language. Running on the transmitter FPGA.
Turbo
- 基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
Turbo
- 一种新的turbo码的交织编码器的vhdl设计，用的是螺旋输入。-something about turbo
TurbojiaozhiVHDL
- 一种基于turbo码的交织器设计，运用vhdl语言。-something about turbo。
rom
- Turbo码编码器的Rom宏模块，此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
interleaver
- 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
interleaver
- 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
inter_ram
- 交织的硬件实现，VERILOG编写的，很有参考价值-Interwoven hardware implementation, VERILOG written of great reference value to
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
基于VHDL卷积交织器的设计与实现
- 基于VHDL卷积交织器的设计与实现(1)(Design and implementation of convolution Interleaver Based on VHDL)